Supports partitioning across heterogenous eFPGA e.g. LUTs, DSP blocks, and Block RAM
Leverage our Continuous Benchmarking System to use our standard benchmark designs or use your own to determine the eFPGA architecture and size that will work for you.
Step 2: Defining the Right eFPGA IP for You
With the results from the Evaluation phase, QuickLogic’s Australis tool will help optimize your eFPGA Logic Array to meet performance and area requirements
Define the type of Logic, RAMs, DSPs and how they will combine into your custom eFPGA IP
Define your eFPGA array size and aspect ratio that suits your SoC/ASIC floorplan
Create your eFPGA to ASIC port mapping for integration
Step 3: Australis Generates Your IP Files
With the results from the Evaluation phase, QuickLogic’s Australis tool will help optimize your eFPGA Logic Array to meet performance and area requirements
Define the type of Logic, RAMs, DSPs and how they will combine into your custom eFPGA IP
Define your eFPGA array size and aspect ratio that suits your SoC/ASIC floorplan
Create your eFPGA to ASIC port mapping for integration
Step 4: Integrate Your eFPGA Into Your SoC
Meet your design goals – for performance, cost and time-to-market.
QuickLogic’s highly experienced FPGA design team will reduce your project risk by supporting you in the integration of the eFPGA IP into your own chip development flow, including test vector generation.
Step 5: Freedom to Innovate
Our support doesn’t end after you go to production with your new eFPGA-enabled semiconductor device.
Target your custom eFPGA with SymbiFlow 100% Open Source OR optional support for advanced features within QuickLogic’s Aurora FPGA User Tools
Faster Run Time & Integrated Timing Analysis Tools
The tools are continually advancing so that you can focus on innovating and drive value for your customers
We use cookies to ensure that we give you the best experience on our website. If you continue to use this site we will assume that you are happy with it.Ok
