We just announced our new ArcticPro™ eFPGA initiative. While the “e” stands for “embedded”, it could just as easily stand for “everywhere”, as this program makes our latest FPGA technology available as an IP block to other companies designing SoC devices for the GLOBALFOUNDRIES’ 22FDX process, as well as their 65nm and 40nm process nodes. Given the range of customers using these processes, we could all well see QuickLogic’s eFPGA IP appearing on many different devices from many different companies addressing a wide range of applications.
At this point you might be asking yourself why an initiative like this makes sense. There are three fundamental reasons. The first is lower cost. As process geometries decrease, mask costs and other design costs are continuing to increase. This means that the addressable market for SoCs designed for advanced nodes must increase in order to keep the amortized development cost as low as possible. eFPGA technology is a great way to do that, by providing post-manufacturing design flexibility for the manufacturer and/or the end user.
The second reason is higher performance. Integrated IP can always have a higher degree of connectivity than discrete devices. Plus, internal connections eliminate the need for big, bulky and complex chip-to-chip I/Os (such as SERDES and the PHYs associated with them and many other communications protocols). Many internal connections running at high speed translate into higher total system performance.
The third reason (and most important for many mobile applications) is lower power. Our FPGA technology has been specifically designed from the ground up for lower power. However, there are other power savings as well. By integrating the FPGA technology inside of their SoC, manufacturers can save the power associated with pushing signals out through their device I/Os, package pins or balls, PCB traces and then back into another device’s package. Not having to fight all of that parasitic capacitance and inductance saves a significant amount of power.
Another way for SoC manufacturers to save power with embedded FPGAs is by smartly exploiting potential hardware/software trade-offs between their embedded CPU and the now-available programmable logic. Certain functions are best implemented using a CPU-running-software approach, while others can be much more power efficient when implemented in hardware-based CPU accelerators or co-processors. Having that level of flexibility allows system designers to choose the best tool for the job.
Cost, performance, and power have always been three of the most important drivers of the adoption of new semiconductor technology. All three factors have the potential to improve significantly for those who adopt eFPGA technology for their next-generation SoC designs. The future is going to be very exciting, so watch carefully for the coming of the “everywhere” FPGA.
